6.10 External memory controller
The external Static Memory Controller is a module which provides an interface between the system bus and external (off-chip) memory devices. It provides support for up to four independently configurable memory banks (16 MBytes each with byte lane enable control) simultaneously. Each memory banks is capable of supporting SRAM, ROM, Flash EPROM, Burst ROM memory, or some external I/O devices
Each memory bank may be 8, 16, or 32 bits wide.
6.11 General purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.
6.12 10-bit A/D converter
The LPC2292/LPC2294 each contain single 10-bit successive approximation analog to digital converter with eight multiplexed channels.
6.13 CAN controllers and acceptance filter
The LPC2292/LPC2294 each contain two/four CAN controllers. The Controller Area network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high speed networks to low cost multiplex wiring.
The LPC2292/LPC2294 each contain two UARTs. One UART provides a full modem control handshake interface, the other provides only transmit and receive data lines.
6.15 I2C serial I/O controller
I2C is a bi-directional bus for inter-IC control using only two wires: a serial
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a
multi-master bus, it can be controlled by more than one bus master connected to it. I2C implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast I2C).
6.16 SPI serial I/O controller
The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master.
6.17 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with
‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
6.18 Watchdog timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the Watchdog within a predetermined amount of time.
6.19 Real time clock
The Real Time Clock (RTC) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
6.20 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2292/LPC2294. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.
Two match registers can be used to provide a single edge controlled PWM output.
One match register (MR0) controls the PWM cycle rate, by resetting the count
upon match. The other match register controls the PWM edge position. Additional
single edge controlled PWM outputs require only one match register each, since
the repetition rate is the same for all PWM outputs. Multiple single edge controlled
PWM outputs will all have a rising edge at the beginning of each PWM cycle,
when an MR0 match occurs.