The LPC2292/LPC2294 are based on a 16/32 bit ARM7TDMI-S™ CPU with real-time emulation and embedded trace support, together with 256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty.

With their 144 pin package, low power consumption, various 32-bit timers, 8-channel
10-bit ADC, 2/4 (LP2292/LPC2294) advanced CAN channels, PWM channels and up to 9 external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and
fault-tolerant maintenance buses. Number of available GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications.

2.1 Key features

16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
16 kB on-chip Static RAM and 256 kB on-chip Flash Program Memory. 128-bit wide interface/accelerator enables high speed 60 MHz operation.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms.
EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software as well as high speed real-time tracing of instruction execution.
Two/four (LPC2292/2294) interconnected CAN interfaces with advanced acceptance filters. Additional serial interfaces include two UARTs (16C550), Fast I2C (400 kbits/s) and two SPIs™.
Eight channel 10-bit A/D converter with conversion time as low as 2.44 ?s.
Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog.
Vectored Interrupt Controller with configurable priorities and vector addresses.
Configurable external memory interface with up to four banks, each up to 16 Mb and 8/16/32 bit data width.
Up to 112 general purpose I/O pins (5 V tolerant). Up to 9 edge/level sensitive external interrupt pins available.

60 MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop.
On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
Two low power modes, Idle and Power-down.
Processor wake-up from Power-down mode via external interrupt.
Individual enable/disable of peripheral functions for power optimization.
Dual power supply:
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V ?0.15 V).
I/O power supply range of 3.0 V to 3.6 V (3.3 V ?10%) with 5 V tolerant I/O
pads.

6. Functional description

Details of the LPC2292/LPC2294 systems and peripheral functions are described in the following sections.

6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and
cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.

The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit THUMB set.

The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.

THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-Chip Flash program memory
The LPC2292/LPC2294 incorporate a 256 kB Flash memory system respectively. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. When on-chip bootloader is used, 248 kB of Flash memory is available for user code.

6.3 On-Chip static RAM
On-Chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2292/LPC2294 provide 16 kB of static RAM.

6.4 Memory map
The LPC2292/LPC2294 memory maps incorporate several distinct regions, as shown in the following figures.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either Flash memory (the default) or on-chip static RAM. This is described in Section
6.21 “System control”.
6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.