- 8051 pin- and instruction set-compatible
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM

On-chip Memory
- 8 kB EPROM (OTP & Windowed Packages)
- 1 kB extra on-chip SRAM for MOVX access
On-chip Analog to Digital Converter
- Eight channels of analog input, 10-bit resolution
- Fast conversion time
Pulse-Width Modulator Outputs
- Four channels of 8-bit PWM
- Channels cascadable to 16-bit PWM Four capture plus three compare registers
55 I/O Port Pins
New Dual Data Pointer Operation
- Either data pointer can be incremented or decremented
- Sets effective on-chip ROM size from 0 - 8kB
- Allows access to entire external memory map
- Dynamically adjustable by software
High-Speed Architecture
- 4 clocks/machine cycle (8051 = 12)
- Runs DC to 33MHz clock rates
- Single-cycle instruction in 121 ns
- New Stretch Cycle feature allows access to fast/slow memory or peripherals
Unique Power Savings Modes
EMI Reduction Mode disables ALE if not needed
High integration controller includes:
- Power-fail reset
- Early-warning power-fail interrupt
- Two full-duplex hardware serial ports
- Programmable watchdog timer
16 total interrupt sources with six external
Available in 68-pin PLCC, 80-pin PQFP, and
68-pin windowed CLCC

The DS87C550 is a fully static, CMOS 8051-compatible microcontroller designed for high performance. While remaining familiar to 8051 family users, it has many new features. With very few exceptions, software written for existing 8051-based systems works without modification on the DS87C550. The exception is critical timing since the High Speed Micro performs its instructions much faster than the original for any given crystal selection. The DS87C550 runs the standard 8051 family instruction set and is pin-compatible with existing devices with similar features in PLCC or QFP packages.
The DS87C550 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051 product. Timers default to a 12 clock per cycle operation to keep their timing compatible with original 8051 family systems. However, timers are individually programmable to run at the new 4 clocks per cycle if desired.

The DS87C550 provides several new hardware features implemented by new Special Function Registers. A summary of all SFRs is provided in Table 2.

The DS87C550 features a high-speed, 8051-compatible core. Higher speed comes not just from increasing the clock frequency, but also from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C550, the same machine cycle takes 4 clocks. Thus the fastest instruction, 1 machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS87C550 will see the full 3 to 1 speed improvement. However, some instructions will achieve between 1.5 and 2.4 to 1 improvement. Regardless of specific performance improvements, all instructions are faster than the original 8051.

The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of individual programs will depend on the actual mix of instructions used. Speed sensitive applications would make the most use of instructions that are 3 times faster. However, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any arbitrary combination of instructions. These architecture improvements and the sub-micron CMOS design produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory.

All instructions in the DS87C550 perform exactly the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks.
For absolute timing of real-time events, the timing of software loops can be calculated using a table in the High Speed Micro User’s Guide. However, counter/timers default to run at the old 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation.

The relative time of two instructions might be different in the new architecture than it was previously. For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct”

instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS87C550, the MOVX instruction takes as little as two machine cycles or eight oscillator cycles, but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS87C550 usually uses one instruction cycle for each instruction byte. Examine the timing of each instruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the original architecture, all were one or two cycles except for MUL and DIV. Refer to the High Speed Micro User’s Guide for details and individual instruction timing.